`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:45:18 09/12/2012
// Design Name:   comparador
// Module Name:   C:/Users/maye/Desktop/taller/lab2/lab3/comparador_prueba.v
// Project Name:  lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: comparador
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module comparador_prueba;

	// Inputs
	reg reset_i;
	reg [3:0] dato_mux_i;
	reg [3:0] dato_mem_i;
	reg clk_i;
	reg start_i;

	// Outputs
	wire [1:0] salida_leds;

	// Instantiate the Unit Under Test (UUT)
	comparador uut (
		.reset_i(reset_i), 
		.dato_mux_i(dato_mux_i), 
		.dato_mem_i(dato_mem_i), 
		.clk_i(clk_i), 
		.salida_leds(salida_leds), 
		.start_i(start_i)
	);
	always begin
	#50 clk_i = ~clk_i;
	end
	always begin
	#89 start_i = ~start_i;
	end

	initial begin
		// Initialize Inputs
		reset_i = 0;
		dato_mux_i = 4;
		dato_mem_i = 6;
		clk_i = 0;
		start_i = 0;

		// Wait 100 ns for global reset to finish
		#1000;
		dato_mem_i = 4;
        
		// Add stimulus here

	end
      
endmodule

